diff options
| author | Andrew Waterman <andrew@sifive.com> | 2018-07-15 22:42:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-07-15 22:42:06 -0700 |
| commit | 636bd8dd9d9cc912c46f5c2efab983e8947d7d0f (patch) | |
| tree | 165bb2ee75459c6ac2026d2412f33cd8c81d834d /src/rv64.tex | |
| parent | 4cbdcd713fa638de28f4b1a43cbbc1be1877c875 (diff) | |
| download | riscv-isa-manual-636bd8dd9d9cc912c46f5c2efab983e8947d7d0f.zip riscv-isa-manual-636bd8dd9d9cc912c46f5c2efab983e8947d7d0f.tar.gz riscv-isa-manual-636bd8dd9d9cc912c46f5c2efab983e8947d7d0f.tar.bz2 | |
More work on HINTs
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index df5db20..bac88cb 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -251,3 +251,57 @@ RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the {\tt cycle}, {\tt time}, and {\tt instret} counters. Hence, the RDCYCLEH, RDTIMEH, and RDINSTRETH instructions are not necessary and are illegal in RV64I. + +\section{HINT Instructions} +\label{sec:rv64i-hints} + +All instructions that are microarchitectural HINTs in RV32I (see +Section~\ref{sec:rv32i-hints}) are also HINTs in RV64I. The +additional computational instructions in RV64I expand both the standard and +custom HINT encoding spaces. + +Table~\ref{tab:rv64i-hints} lists all RV64I HINT code points. 91\% of the HINT +space is reserved for standard HINTs, but none are presently defined. The +remainder of the HINT space is reserved for custom HINTs: no standard HINTs +will ever be defined in this subspace. + +\begin{table}[hbt] +\centering +\begin{tabular}{|l|l|c|l|} + \hline + Instruction & Constraints & Code Points & Purpose \\ \hline \hline + LUI & {\em rd}={\tt x0} & $2^{20}$ & \multirow{21}{*}{\em Reserved for future standard use} \\ \cline{1-3} + AUIPC & {\em rd}={\tt x0} & $2^{20}$ & \\ \cline{1-3} + \multirow{2}{*}{ADDI} & {\em rd}={\tt x0}, and either & \multirow{2}{*}{$2^{17}-1$} & \\ + & {\em rs1}$\neq${\tt x0} or {\em imm}$\neq$0 & & \\ \cline{1-3} + ANDI & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3} + ORI & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3} + XORI & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3} + ADDIW & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3} + ADD & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SUB & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + AND & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + OR & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + XOR & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SLL & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRL & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRA & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + ADDW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SUBW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SLLW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRLW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRAW & {\em rd}={\tt x0} & $2^{10}$ & \\ \hline \hline + SLTI & {\em rd}={\tt x0} & $2^{17}$ & \multirow{10}{*}{\em Reserved for custom use} \\ \cline{1-3} + SLTIU & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3} + SLLI & {\em rd}={\tt x0} & $2^{11}$ & \\ \cline{1-3} + SRLI & {\em rd}={\tt x0} & $2^{11}$ & \\ \cline{1-3} + SRAI & {\em rd}={\tt x0} & $2^{11}$ & \\ \cline{1-3} + SLLIW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRLIW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SRAIW & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SLT & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3} + SLTU & {\em rd}={\tt x0} & $2^{10}$ & \\ \hline +\end{tabular} +\caption{RV64I HINT instructions.} +\label{tab:rv64i-hints} +\end{table} |