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| author | Andrew Waterman <andrew@sifive.com> | 2018-07-15 20:48:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-07-15 20:48:39 -0700 |
| commit | 4cbdcd713fa638de28f4b1a43cbbc1be1877c875 (patch) | |
| tree | e8c652f262c05d702508957f0c8a5cfac6f8bed4 /src/rv64.tex | |
| parent | 1b92dfcdf10496b4853da07fd7fda8ec2c6f5955 (diff) | |
| download | riscv-isa-manual-4cbdcd713fa638de28f4b1a43cbbc1be1877c875.zip riscv-isa-manual-4cbdcd713fa638de28f4b1a43cbbc1be1877c875.tar.gz riscv-isa-manual-4cbdcd713fa638de28f4b1a43cbbc1be1877c875.tar.bz2 | |
Fix spelling of "pseudoinstruction"
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index 903c1dc..df5db20 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -61,7 +61,7 @@ immediate to register {\em rs1} and produces the proper sign-extension of a 32-bit result in {\em rd}. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW {\em rd, rs1, 0} writes the sign-extension of the lower 32 bits -of register {\em rs1} into register {\em rd} (assembler psuedo-instruction +of register {\em rs1} into register {\em rd} (assembler pseudoinstruction SEXT.W). \vspace{-0.2in} |