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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:43:16 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:43:16 -0700 |
| commit | 0ebf86910b43ee87d08c4cabe136d464541e1ac0 (patch) | |
| tree | 98837764d3b7ccb5c9b53083e5328b8f007f8114 /src/rv64.tex | |
| parent | 61cadb9df80baac7e6da6574f7b81d8e8d97f283 (diff) | |
| download | riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.zip riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.tar.gz riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.tar.bz2 | |
Moved CSR instructions into separate chapter.
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index bac88cb..e4bfb3c 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -244,14 +244,6 @@ values, as are LB and LBU for 8-bit values. The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register {\em rs2} to memory respectively. -\section{System Instructions} - -In RV64I, the CSR instructions can manipulate 64-bit CSRs. In particular, the -RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of -the {\tt cycle}, {\tt time}, and {\tt instret} counters. Hence, the RDCYCLEH, -RDTIMEH, and RDINSTRETH instructions are not necessary and are illegal in -RV64I. - \section{HINT Instructions} \label{sec:rv64i-hints} |