Chapter 7 updates.

Updated all the wavedrom to match LaTeX versions.
Removed figure titles.
Update table to match LaTeX.
Cleaned up conversion breakage.

1 files changed, 13 insertions, 15 deletions

diff --git a/src/rv64.adoc b/src/rv64.adoc
index 3e90eb3..602d81e 100644
--- a/src/rv64.adoc
+++ b/src/rv64.adoc
@@ -9,7 +9,7 @@ in conjunction with the earlier chapter.
 === Register State
 
 RV64I widens the integer registers and supported user address space to
-64 bits (XLEN=64 in <<gprs>>.
+64 bits (XLEN=64 in <<gprs>>).
 
 === Integer Computational Instructions
 
@@ -41,8 +41,7 @@ ensure reasonable performance for 32-bit values.
 
 include::images/wavedrom/rv64i-base-int.adoc[]
 [[rv64i-base-int]]
-.RV64I register-immediate instructions
-image::image_placeholder.png[]
+//.RV64I register-immediate instructions
 
 ADDIW is an RV64I instruction that adds the sign-extended 12-bit
 immediate to register _rs1_ and produces the proper sign-extension of a
@@ -50,12 +49,10 @@ immediate to register _rs1_ and produces the proper sign-extension of a
 32 bits of the result sign-extended to 64 bits. Note, ADDIW _rd, rs1, 0_
 writes the sign-extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
-//the following diagram doesn't match the tex spec
 
 include::images/wavedrom/rv64i-addiw.adoc[]
 [[rv64i-addiw]]
-.RV64I register-immediate (descr ADDIW) instructions
-image::image_placeholder.png[]
+//.RV64I register-immediate (descr ADDIW) instructions
 
 Shifts by a constant are encoded as a specialization of the I-type
 format using the same instruction opcode as RV32I. The operand to be
@@ -84,8 +81,7 @@ are marked as reserved. This is a backwards-compatible change.
 
 include::images/wavedrom/rv64_lui-auipc.adoc[]
 [[rv64_lui-auipc]]
-.RV64I register-immediate (descr) instructions
-image::image_placeholder.png[]
+//.RV64I register-immediate (descr) instructions
 
 LUI (load upper immediate) uses the same opcode as RV32I. LUI places the
 32-bit U-immediate into register _rd_, filling in the lowest 12 bits
@@ -111,8 +107,7 @@ with LD, AUIPC with JALR, etc.in RV64I is
 //this diagramdoesn't match the tex specification
 include::images/wavedrom/rv64i_int-reg-reg.adoc[]
 [[int_reg-reg]]
-.RV64I integer register-register instructions
-image::image_placeholder.png[]
+//.RV64I integer register-register instructions
 
 ADDW and SUBW are RV64I-only instructions that are defined analogously
 to ADD and SUB but operate on 32-bit values and produce signed 32-bit
@@ -140,8 +135,7 @@ will define what portions of the address space are legal to access.
 
 include::images/wavedrom/load_store.adoc[]
 [[load_store]]
-.Load and store instructions
-image::image_placeholder.png[]
+//.Load and store instructions
 
 The LD instruction loads a 64-bit value from memory into register _rd_
 for RV64I.
@@ -171,10 +165,10 @@ no standard HINTs will ever be defined in this subspace.
 
 [[rv64i-h]]
 .RV64I HINT instructions.
-[options="header",]
+[cols="~,~,~,~", options="header", grid="all"]
 |===
 |Instruction |Constraints |Code Points |Purpose
-|LUI |_rd_=_x0_ |latexmath:[$2^{20}$] .24+.^|_Reserved for future standard use_
+|LUI |_rd_=_x0_ |latexmath:[$2^{20}$] .9+.^|_Reserved for future standard use_
 
 |AUIPC |_rd_=_x0_ |latexmath:[$2^{20}$]
 
@@ -188,7 +182,11 @@ no standard HINTs will ever be defined in this subspace.
 
 |ADDIW |_rd_=_x0_ |latexmath:[$2^{17}$]
 
-|ADD |_rd_=_x0_ |latexmath:[$2^{10}$]
+|ADD |_rd_=_x0_, _rs1_latexmath:[$\neq$]_x0_ |latexmath:[$2^{10}$]
+
+|Add |_rd_=_x0_, _rs1_=_x0_, _rs2_latexmath:[$\neq$]_x2_-_x5_| 28
+
+|Add |_rd_=_x0_, _rs1_=_x0_, _rs2_=_x2_-_x5_| 4 a| (_rs2_=_x2_) NTL.P1<br />  (_rs2_=_x3_) NTL.PALL (_rs2_=_x4_) NTL.S1 (_rs2_=_x5_) NTL.ALL
 
 |SUB |_rd_=_x0_ |latexmath:[$2^{10}$]