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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:43:16 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:43:16 -0700 |
| commit | 0ebf86910b43ee87d08c4cabe136d464541e1ac0 (patch) | |
| tree | 98837764d3b7ccb5c9b53083e5328b8f007f8114 /src/rv32e.tex | |
| parent | 61cadb9df80baac7e6da6574f7b81d8e8d97f283 (diff) | |
| download | riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.zip riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.tar.gz riscv-isa-manual-0ebf86910b43ee87d08c4cabe136d464541e1ac0.tar.bz2 | |
Moved CSR instructions into separate chapter.
Diffstat (limited to 'src/rv32e.tex')
| -rw-r--r-- | src/rv32e.tex | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/rv32e.tex b/src/rv32e.tex index 2c08be5..7682f03 100644 --- a/src/rv32e.tex +++ b/src/rv32e.tex @@ -50,15 +50,6 @@ bits freed up by the reduced register-specifier fields and so these are available for non-standard extensions. \end{commentary} -A further simplification is that the counter instructions ({\tt - rdcycle[h]},{\tt rdtime[h]}, {\tt rdinstret[h]}) are no longer -mandatory. - -\begin{commentary} -The mandatory counters require additional registers and logic, and can -be replaced with more application-specific facilities. -\end{commentary} - \section{RV32E Extensions} RV32E can be extended with the M, A, and C user-level standard extensions. |