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| author | Andrew Waterman <andrew@sifive.com> | 2020-04-16 18:43:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-04-16 18:43:34 -0700 |
| commit | a2ae53f289802e8857516404ab8d2591d614aedb (patch) | |
| tree | ee30a4f5da101d5ba753f4f47e9d54da373e10e2 /src/rv32.tex | |
| parent | 470a973251cd719786d990920e1a34858ba9e99c (diff) | |
| download | riscv-isa-manual-a2ae53f289802e8857516404ab8d2591d614aedb.zip riscv-isa-manual-a2ae53f289802e8857516404ab8d2591d614aedb.tar.gz riscv-isa-manual-a2ae53f289802e8857516404ab8d2591d614aedb.tar.bz2 | |
Make misaligned exception text more generic than RV32
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index fbafdae..dc5e36d 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1088,9 +1088,9 @@ store 32-bit, 16-bit, and 8-bit values from the low bits of register Regardless of EEI, loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception. -Loads and stores where the effective address is not naturally aligned -to the referenced datatype (i.e., on a four-byte boundary for 32-bit -accesses, and a two-byte boundary for 16-bit accesses) have behavior +Loads and stores whose effective address is not naturally aligned +to the referenced datatype (i.e., the effective address is +not divisible by the size of the access in bytes) have behavior dependent on the EEI. An EEI may guarantee that misaligned loads and stores are fully |