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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-20 14:09:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-20 14:09:05 -0800 |
| commit | 9c98df74ee8bddbbdd0d1f09c8cc8b99d526b274 (patch) | |
| tree | 7e7e0e3f8b2ba5fdde3d0d159a8a61e3c8fc1f7c /src/rv32.tex | |
| parent | 3a8c4ed2eec4a325690feaf0a00f81c2283853d9 (diff) | |
| download | riscv-isa-manual-9c98df74ee8bddbbdd0d1f09c8cc8b99d526b274.zip riscv-isa-manual-9c98df74ee8bddbbdd0d1f09c8cc8b99d526b274.tar.gz riscv-isa-manual-9c98df74ee8bddbbdd0d1f09c8cc8b99d526b274.tar.bz2 | |
tweaks
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index cc64b33..7b6368d 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -43,10 +43,11 @@ holds the address of the current instruction. \begin{commentary} There is no dedicated stack pointer or subroutine return address link -register in the Base Integer ISA, the instruction encoding allows any -{\tt x} register to be used for these purposes. However the standard +register in the Base Integer ISA; the instruction encoding allows any +{\tt x} register to be used for these purposes. However, the standard software calling convention uses register {\tt x1} to hold the return -address for a call, with register {\tt x5} available as an alternate. +address for a call, with register {\tt x5} available as an alternate +link register. The standard calling convention uses register {\tt x2} as the stack pointer. @@ -57,7 +58,7 @@ instructions. The optional compressed 16-bit instruction format is designed around the assumption that {\tt x1} is the return address register and {\tt x2} is the stack pointer. Software using other conventions will -operate correctly but may not gain as much code compression. +operate correctly but may have greater code size. The number of available architectural registers can have large impacts on code size, performance, and energy consumption. Although 16 |