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| author | Paul Donahue <pdonahue@ventanamicro.com> | 2019-05-01 10:46:18 -0700 |
|---|---|---|
| committer | Paul Donahue <pdonahue@ventanamicro.com> | 2019-05-01 10:46:18 -0700 |
| commit | 830229b0259d55d3a98b6d2f5a9cd436df4c040c (patch) | |
| tree | 77be45c2b824007c669ec457eb7de02d65c6f40e /src/rv32.tex | |
| parent | 53d14bac028db4bb8c0fe3cfa5a89e191c5e157c (diff) | |
| download | riscv-isa-manual-830229b0259d55d3a98b6d2f5a9cd436df4c040c.zip riscv-isa-manual-830229b0259d55d3a98b6d2f5a9cd436df4c040c.tar.gz riscv-isa-manual-830229b0259d55d3a98b6d2f5a9cd436df4c040c.tar.bz2 | |
Introduce the term UNSPECIFIED.
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index b6885cb..98a9d7a 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -162,6 +162,8 @@ and to simplify hardware design for systems with IALIGN=32, where these are the only places where misalignment can occur. \end{commentary} +The behavior when decoding a reserved instruction is UNSPECIFIED. + \vspace{-0.2in} \begin{figure}[h] \begin{center} |