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| author | Andrew Waterman <andrew@sifive.com> | 2020-04-16 17:55:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-04-16 17:55:36 -0700 |
| commit | 470a973251cd719786d990920e1a34858ba9e99c (patch) | |
| tree | 6ca7e22a8a658231be6f183ee4ef4ce69f55d848 /src/rv32.tex | |
| parent | baea02550976abe89db299bfff01e9ef82b269a3 (diff) | |
| download | riscv-isa-manual-470a973251cd719786d990920e1a34858ba9e99c.zip riscv-isa-manual-470a973251cd719786d990920e1a34858ba9e99c.tar.gz riscv-isa-manual-470a973251cd719786d990920e1a34858ba9e99c.tar.bz2 | |
Clarify that the EEI defines misaligned FP ld/st behavior
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 67b2cbc..fbafdae 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -994,6 +994,7 @@ compressed instruction-set extension, C. \end{commentary} \section{Load and Store Instructions} +\label{sec:rv32:ldst} RV32I is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on |