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| author | Bruce Hoult <bruce@hoult.org> | 2018-12-19 22:38:26 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-19 22:53:36 -0800 |
| commit | 3bb14a59f00de1107a7c6983d0ae80b72d320c69 (patch) | |
| tree | 6206b9982b7146ef41782b46aa3c0a89efebe7ae /src/rv32.tex | |
| parent | f5197210a04dc54564f7a9e1be267c6ade049eb6 (diff) | |
| download | riscv-isa-manual-3bb14a59f00de1107a7c6983d0ae80b72d320c69.zip riscv-isa-manual-3bb14a59f00de1107a7c6983d0ae80b72d320c69.tar.gz riscv-isa-manual-3bb14a59f00de1107a7c6983d0ae80b72d320c69.tar.bz2 | |
Update commentary to reflect MIPS r6 conditional branches
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 9ea0e8a..a29fc66 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -891,8 +891,8 @@ conditional-branch prediction tables. \begin{commentary} The conditional branches were designed to include arithmetic -comparison operations between two registers (as also done in PA-RISC -and Xtensa ISA), rather than use condition codes (x86, ARM, SPARC, +comparison operations between two registers (as also done in PA-RISC, +Xtensa, and MIPS R6), rather than use condition codes (x86, ARM, SPARC, PowerPC), or to only compare one register against zero (Alpha, MIPS), or two registers only for equality (MIPS). This design was motivated by the observation that a combined compare-and-branch instruction fits |