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| author | Andrew Waterman <andrew@sifive.com> | 2019-08-04 15:40:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-02 17:25:50 +0200 |
| commit | 085e82492c61675254b4553ea084c570e8f2b60c (patch) | |
| tree | a9b6678a7a87ec508d5cb1e43fd4a066255e981c /src/rv32.tex | |
| parent | a4c6b9f7d2ba139bd1ad8b5d66da8a0a0b0aba4d (diff) | |
| download | riscv-isa-manual-085e82492c61675254b4553ea084c570e8f2b60c.zip riscv-isa-manual-085e82492c61675254b4553ea084c570e8f2b60c.tar.gz riscv-isa-manual-085e82492c61675254b4553ea084c570e8f2b60c.tar.bz2 | |
Use effective address consistently
Diffstat (limited to 'src/rv32.tex')
| -rw-r--r-- | src/rv32.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index 233109a..1548dc0 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1038,7 +1038,7 @@ offset[11:5] & src & base & width & offset[4:0] & STORE \\ Load and store instructions transfer a value between the registers and memory. Loads are encoded in the I-type format and stores are -S-type. The effective byte address is obtained by adding register +S-type. The effective address is obtained by adding register {\em rs1} to the sign-extended 12-bit offset. Loads copy a value from memory to register {\em rd}. Stores copy the value in register {\em rs2} to memory. |