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author | Andrew Waterman <andrew@sifive.com> | 2018-12-11 14:49:31 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-12-11 14:52:07 -0800 |
commit | 5eb0b27c814037999fcf74b6b4e13c15782d2089 (patch) | |
tree | 6ba0a1fb0e57cf4fa391ce7ef7c25afd6015c401 /src/rv32.tex | |
parent | 3d804e0f123a27c887753a52b44ac964b0d3855e (diff) | |
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Restate that conditional branches can raise misaligned exceptions in RVI
This is a bit redundant, since we state this at the front of the chapter. But
since we also restate it for JAL/JALR, it's better to maintain symmetry and
restate it for branches, too.
Closes #303
h/t @benjaminselfridge
Diffstat (limited to 'src/rv32.tex')
-rw-r--r-- | src/rv32.tex | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index ced9826..a7623bb 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -946,6 +946,18 @@ allowing the branch and following instructions to be executed speculatively and out-of-order with respect to other code~\cite{ibmpower7}. \end{commentary} +The conditional branch instructions will generate an +instruction-address-misaligned exception if the target address is not +aligned to a four-byte boundary and the branch condition evaluates +to true. If the branch condition evaluates to false, the +instruction-address-misaligned exception will not be raised. + +\begin{commentary} +Instruction-address-misaligned exceptions are not possible on machines +that support extensions with 16-bit aligned instructions, such as the +compressed instruction-set extension, C. +\end{commentary} + \section{Load and Store Instructions} RV32I is a load-store architecture, where only load and store |