Removed extraneous italic formatting.

Remove italic formattion of admonition as that's handled in the theme.
Removed ref alt text as that's in the theme.

1 files changed, 12 insertions, 12 deletions

diff --git a/src/rv32.adoc b/src/rv32.adoc
index cd229ea..0fdd1e6 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -92,23 +92,23 @@ holds the address of the current instruction.
 |===
 [NOTE]
 ====
-_There is no dedicated stack pointer or subroutine return address link
+There is no dedicated stack pointer or subroutine return address link
 register in the Base Integer ISA; the instruction encoding allows any
 `x` register to be used for these purposes. However, the standard
 software calling convention uses register `x1` to hold the return
 address for a call, with register `x5` available as an alternate link
 register. The standard calling convention uses register `x2` as the
-stack pointer._
+stack pointer.
 
-_Hardware might choose to accelerate function calls and returns that use
-`x1` or `x5`. See the descriptions of the JAL and JALR instructions._
+Hardware might choose to accelerate function calls and returns that use
+`x1` or `x5`. See the descriptions of the JAL and JALR instructions.
 
-_The optional compressed 16-bit instruction format is designed around the
+The optional compressed 16-bit instruction format is designed around the
 assumption that `x1` is the return address register and `x2` is the
 stack pointer. Software using other conventions will operate correctly
-but may have greater code size._
+but may have greater code size.
 
-_The number of available architectural registers can have large impacts
+The number of available architectural registers can have large impacts
 on code size, performance, and energy consumption. Although 16 registers
 would arguably be sufficient for an integer ISA running compiled code,
 it is impossible to encode a complete ISA with 16 registers in 16-bit
@@ -119,20 +119,20 @@ We wanted to avoid intermediate instruction sizes (such as Xtensa's
 a 32-bit instruction size was adopted, it was straightforward to support
 32 integer registers. A larger number of integer registers also helps
 performance on high-performance code, where there can be extensive use
-of loop unrolling, software pipelining, and cache tiling._
+of loop unrolling, software pipelining, and cache tiling.
 
-_For these reasons, we chose a conventional size of 32 integer registers
+For these reasons, we chose a conventional size of 32 integer registers
 for RV32I. Dynamic register usage tends to be dominated by a few
 frequently accessed registers, and regfile implementations can be
 optimized to reduce access energy for the frequently accessed
 registers. The optional compressed 16-bit instruction format mostly
 only accesses 8 registers and hence can provide a dense instruction
 encoding, while additional instruction-set extensions could support a
-much larger register space (either flat or hierarchical) if desired._
+much larger register space (either flat or hierarchical) if desired.
 
-_For resource-constrained embedded applications, we have defined the
+For resource-constrained embedded applications, we have defined the
 RV32E subset, which only has 16 registers
-(<<rv32e, Chapter 6>>)._
+(<<rv32e>>).
 ====
 === Base Instruction Formats