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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-08 00:02:16 -0700 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-08 00:02:16 -0700 |
| commit | ca1850e125a77b3a6b9b8a80e3cdc30f3d74a584 (patch) | |
| tree | aba73f0412338e1feb8d70da8dc2e3e8b95daadc /src/rv128.tex | |
| parent | 3536b679c4fcfb2cf833302d1bf960864b4c4a66 (diff) | |
| download | riscv-isa-manual-ca1850e125a77b3a6b9b8a80e3cdc30f3d74a584.zip riscv-isa-manual-ca1850e125a77b3a6b9b8a80e3cdc30f3d74a584.tar.gz riscv-isa-manual-ca1850e125a77b3a6b9b8a80e3cdc30f3d74a584.tar.bz2 | |
Fix spelling errors
Diffstat (limited to 'src/rv128.tex')
| -rw-r--r-- | src/rv128.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv128.tex b/src/rv128.tex index ef78dd9..64515e3 100644 --- a/src/rv128.tex +++ b/src/rv128.tex @@ -48,7 +48,7 @@ added. The ``*D'' instructions consume two major opcodes (OP-IMM-64 and OP-64) in the standard 32-bit encoding. \begin{commentary} - To improve compatibilty with RV64, in a reverse of how RV32 to RV64 + To improve compatibility with RV64, in a reverse of how RV32 to RV64 was handled, we might change the decoding around to rename RV64I ADD as a 64-bit ADDD, and add a 128-bit ADDQ in what was previously the OP-64 major opcode (now renamed the OP-128 major opcode). |