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author | Bill Traynor <wmat@riscv.org> | 2023-03-10 16:48:23 -0500 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-03-10 16:48:23 -0500 |
commit | f16e42bdbdcebc27ba4197f8299e1b8cffe30744 (patch) | |
tree | 9c09a4277d3075521f6b84b9eb01d76ae7a85c68 /src/rnmi.adoc | |
parent | eb5e542cc908471718858d5ddc4e58bbc1f70066 (diff) | |
download | riscv-isa-manual-f16e42bdbdcebc27ba4197f8299e1b8cffe30744.zip riscv-isa-manual-f16e42bdbdcebc27ba4197f8299e1b8cffe30744.tar.gz riscv-isa-manual-f16e42bdbdcebc27ba4197f8299e1b8cffe30744.tar.bz2 |
Added missing admonitions
Adding in missing admonitions.
Diffstat (limited to 'src/rnmi.adoc')
-rw-r--r-- | src/rnmi.adoc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc index fe8cd21..088c4e6 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -93,13 +93,20 @@ regardless of the current setting of `mstatus`.MPRV. Upon reset, NMIE contains the value 0. +[NOTE] +==== RNMIs are masked out of reset to give software the opportunity to initialize data structures and devices for subsequent RNMI handling. +==== Software can set NMIE to 1, but attempts to clear NMIE have no effect. +[NOTE] +==== Normally, only reset sequences will explicitly set the NMIE bit. +*** + That the NMIE bit is settable does not suffice to support the nesting of RNMIs. To support this feature in a direct manner would have required allowing software to clear the NMIE bit—a design choice that would have @@ -109,6 +116,7 @@ Software that wishes to minimize the latency until the next RNMI is taken can follow the top-half/bottom-half model, where the RNMI handler itself only enqueues a task to a task queue then returns. The bulk of the interrupt servicing is performed later, with RNMIs enabled. +==== For the purposes of the WFI instruction, NMIE is a global interrupt enable, meaning that the setting of NMIE does not affect the operation @@ -144,7 +152,10 @@ while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address (rather than the address specified by `mtvec`). +[NOTE] +==== The Smrnmi extension does not change the behavior of the MRET and SRET instructions. In particular, MRET and SRET are unaffected by the `mnstatus`.NMIE bit, and their execution does not alter the `mnstatus`.NMIE bit. +====
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