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authorAndrew Waterman <andrew@sifive.com>2024-02-20 18:07:55 -0800
committerAndrew Waterman <andrew@sifive.com>2024-02-29 15:39:17 -0800
commit10700d0766501c9a4ce16c7cab53c908c44d5158 (patch)
treeaaa3715d879802bb47e89e72f06cf5d3899e7aaf /src/rnmi.adoc
parent98918c844281332f4e75ad7d4c818ad9ecaeb5ad (diff)
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Update Smrnmi to account for Smdbltrp extension
This is a backwards compatible change to support resumable double traps within M-mode when both extensions are implemented. Although the resumability feature is not terribly interesting, the reuse of the Smrnmi state for M-mode double traps aids debugging (and fault diagnosis for the hardware-error exception case).
Diffstat (limited to 'src/rnmi.adoc')
-rw-r--r--src/rnmi.adoc12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc
index 9938917..cbd19da 100644
--- a/src/rnmi.adoc
+++ b/src/rnmi.adoc
@@ -71,9 +71,15 @@ of holding.
.Resumable NMI cause `mncause`.
include::images/bytefield/mncause.edn[]
-The `mncause` CSR holds the reason for the NMI, with bit MXLEN-1 set to
-1, and the NMI cause encoded in the least-significant bits or zero if
-NMI causes are not supported.
+The `mncause` CSR holds the reason for the NMI.
+If the reason is an interrupt, bit MXLEN-1 is set to 1, and the NMI
+cause is encoded in the least-significant bits.
+If the reason is an interrupt and NMI causes are not supported, bit MXLEN-1 is
+set to 1, and zero is written to the least-significant bits.
+If the reason is an exception within M-mode that results in a double trap as
+specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the
+least-significant bits are set to the cause code corresponding to the
+exception that precipitated the double trap.
.Resumable NMI status register `mnstatus`.
include::images/bytefield/mnstatus.edn[]