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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-12 17:06:10 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-12 17:06:10 -0800 |
| commit | cfd8395ce137406ef34f41539962a0907c2bd3a4 (patch) | |
| tree | 03657297bcbe1d841fb08908ca61a6af4c7fc2b8 /src/q.tex | |
| parent | 5eb0b27c814037999fcf74b6b4e13c15782d2089 (diff) | |
| download | riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.zip riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.tar.gz riscv-isa-manual-cfd8395ce137406ef34f41539962a0907c2bd3a4.tar.bz2 | |
Fix some incorrect references to RV32IF (as opposed to RV32IFZicsr)
Diffstat (limited to 'src/q.tex')
| -rw-r--r-- | src/q.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5,7 +5,7 @@ This chapter describes the Q standard extension for 128-bit quad-precision binar floating-point instructions compliant with the IEEE 754-2008 arithmetic standard. The quad-precision binary floating-point instruction-set extension is named ``Q'', and requires -RV64IFD. The floating-point registers are now extended to hold either +RV64IFDZicsr. The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128). The NaN-boxing scheme described in Section~\ref{nanboxing} is now extended recursively to allow a single-precision value to be NaN-boxed |