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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-07 23:21:47 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-07 23:21:47 -0700 |
| commit | ce5e74a66ea22327702eca09e7a868db7e9615e9 (patch) | |
| tree | 680316ba9cf8961f823891e6acc3e0fc54fd26f7 /src/q.tex | |
| parent | 627495d8a6935b03f3c09164f27a67393ef3173d (diff) | |
| download | riscv-isa-manual-ce5e74a66ea22327702eca09e7a868db7e9615e9.zip riscv-isa-manual-ce5e74a66ea22327702eca09e7a868db7e9615e9.tar.gz riscv-isa-manual-ce5e74a66ea22327702eca09e7a868db7e9615e9.tar.bz2 | |
Made cleanup pass over floating-point extensions
Diffstat (limited to 'src/q.tex')
| -rw-r--r-- | src/q.tex | 9 |
1 files changed, 5 insertions, 4 deletions
@@ -79,7 +79,7 @@ Meaning \\ \hline 00 & S & 32-bit single-precision \\ 01 & D & 64-bit double-precision \\ -10 & - & {\em reserved} \\ +10 & H & 16-bit half-precision \\ 11 & Q & 128-bit quad-precision \\ \hline \end{tabular} @@ -233,11 +233,12 @@ FSGNJ & Q & src2 & src1 & J[N]/JX & dest & OP-FP \\ \end{tabular} \end{center} -FMV.X.Q and FMV.Q.X instructions are not provided, so quad-precision bit -patterns must be moved to the integer registers via memory. +FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so +quad-precision bit patterns must be moved to the integer registers via +memory. \begin{commentary} -RV128 supports FMV.X.Q and FMV.Q.X in the Q extension. +RV128 will spuport FMV.X.Q and FMV.Q.X in the Q extension. \end{commentary} \section{Quad-Precision Floating-Point Compare Instructions} |