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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-10 12:21:03 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-10 12:21:03 -0800 |
| commit | bf33d5feb1290448e97fb5bf395c813923573068 (patch) | |
| tree | cc6ebfae4a89658b4270a0af7a9bf769673ad433 /src/q.tex | |
| parent | 42adb492c5b5b3913e20dc84111bc9be3391fb98 (diff) | |
| download | riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.zip riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.tar.gz riscv-isa-manual-bf33d5feb1290448e97fb5bf395c813923573068.tar.bz2 | |
subset -> extension
Diffstat (limited to 'src/q.tex')
| -rw-r--r-- | src/q.tex | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -1,10 +1,10 @@ \chapter{``Q'' Standard Extension for Quad-Precision Floating-Point, Version 2.2} -This chapter describes the Q standard extension for 128-bit binary +This chapter describes the Q standard extension for 128-bit quad-precision binary floating-point instructions compliant with the IEEE 754-2008 -arithmetic standard. The 128-bit or quad-precision binary -floating-point instruction subset is named ``Q'', and requires +arithmetic standard. The quad-precision binary +floating-point instruction-set extension is named ``Q'', and requires RV64IFD. The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128). The NaN-boxing scheme described in Section~\ref{nanboxing} is now |