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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-14 11:41:27 -0800 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-14 11:41:27 -0800 |
| commit | 619b1938bdb2da7fd97853d61e767f455cf2a62a (patch) | |
| tree | 3e273a6429522057bc357548f7bea5b23c5e4846 /src/q.tex | |
| parent | 303d8dde10da6c5ae603ea80ec56aeb9aa3f55e4 (diff) | |
| download | riscv-isa-manual-619b1938bdb2da7fd97853d61e767f455cf2a62a.zip riscv-isa-manual-619b1938bdb2da7fd97853d61e767f455cf2a62a.tar.gz riscv-isa-manual-619b1938bdb2da7fd97853d61e767f455cf2a62a.tar.bz2 | |
ISA extension dependences can be assumed in ISA name strings
Diffstat (limited to 'src/q.tex')
| -rw-r--r-- | src/q.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5,7 +5,7 @@ This chapter describes the Q standard extension for 128-bit quad-precision binar floating-point instructions compliant with the IEEE 754-2008 arithmetic standard. The quad-precision binary floating-point instruction-set extension is named ``Q'', and requires -RV64IFDZicsr. The floating-point registers are now extended to hold either +RV64IFD. The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128). The NaN-boxing scheme described in Section~\ref{nanboxing} is now extended recursively to allow a single-precision value to be NaN-boxed |