Added the NaN-boxing scheme for narrower floating-point values held in wider floating-point values.

1 files changed, 4 insertions, 6 deletions

diff --git a/src/q.tex b/src/q.tex
index 2830cd3..0768d9b 100644
--- a/src/q.tex
+++ b/src/q.tex
@@ -7,6 +7,10 @@ arithmetic standard. The 128-bit or quad-precision binary
 floating-point instruction subset is named ``Q'', and requires
 RV64IFD.  The floating-point registers are now extended to hold either
 a single, double, or quad-precision floating-point value (FLEN=128).
+The NaN-boxing scheme described in Section~\ref{nanboxing} is now
+extended recursively to allow a single-precision value to be NaN-boxed
+inside a double-precision value which is itself NaN-boxed inside a
+quad-precision value.
 
 \section{Quad-Precision Load and Store Instructions}
 
@@ -57,12 +61,6 @@ offset[11:5] & src & base & Q & offset[4:0] & STORE-FP \\
 \end{tabular}
 \end{center}
 
-If a floating-point register holds a single-precision or
-double-precision value, it is guaranteed that a FSQ of that register
-will place a value into memory that when reloaded with a FLQ will
-recreate the original value in a register.  The data format that is
-stored in memory is undefined beyond having this property.
-
 FLQ and FSQ are only guaranteed to execute atomically if the effective address
 is naturally aligned and XLEN=128.