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| author | Bill Traynor <wmat@riscv.org> | 2023-04-06 10:15:32 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-04-06 10:15:32 -0400 |
| commit | fd5719ce4c7c780eb8fed6a18b82c55a7ce3c7ae (patch) | |
| tree | fa317621484e31a56aa718686acaf4058e046b5e /src/priv-preface.adoc | |
| parent | b9a59062b2403f9a4c020c32b9f4e027ea500f52 (diff) | |
| download | riscv-isa-manual-fd5719ce4c7c780eb8fed6a18b82c55a7ce3c7ae.zip riscv-isa-manual-fd5719ce4c7c780eb8fed6a18b82c55a7ce3c7ae.tar.gz riscv-isa-manual-fd5719ce4c7c780eb8fed6a18b82c55a7ce3c7ae.tar.bz2 | |
Fixed formatting.
Fixed up some formatting to match LaTeX spec.
Diffstat (limited to 'src/priv-preface.adoc')
| -rw-r--r-- | src/priv-preface.adoc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index 38f6b43..d49d4d8 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -86,7 +86,7 @@ performed by the implementation. * Clarify the architectural behavior of address-translation caches * Added Sv57 and Sv57x4 address translation modes. * Software breakpoint exceptions are permitted to write either 0 or the -`pc` to _x_`tval`. +`pc` to `__x__tval`. * Clarified that bare S-mode need not support the SFENCE.VMA instruction. * Specified relaxed constraints for implicit reads of non-idempotent @@ -129,15 +129,15 @@ instructions from user pages, regardless of the SUM setting. the possibility of a future global-ASID extension. * SFENCE.VMA semantics have been clarified. * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. -* Made the unused _x_ip fields *WPRI*, rather than *WIRI*. +* Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*. * Made the unused `misa` fields *WARL*, rather than *WIRI*. * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. * Required all harts in a system to employ the same PTE-update scheme as each other. * Rectified an editing error that misdescribed the mechanism by which -`mstatus`. _x_IE is written upon an exception. +`mstatus.__x__IE` is written upon an exception. * Described scheme for emulating misaligned AMOs. -* Specified the behavior of the `misa` and _x_ `epc` registers in systems +* Specified the behavior of the `misa` and `__x__epc` registers in systems with variable IALIGN. * Specified the behavior of writing self-contradictory values to the `misa` register. |