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authorBill Traynor <wmat@riscv.org>2023-01-27 16:36:44 -0500
committerBill Traynor <wmat@riscv.org>2023-01-27 16:36:44 -0500
commitabda5ecc5927b0196568b9ea110a29e001ebd540 (patch)
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Fixed typo.
Fixed a typo.
Diffstat (limited to 'src/priv-preface.adoc')
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diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 832c9aa..b547648 100644
--- a/src/priv-preface.adoc
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@@ -164,7 +164,7 @@ redundancy and offloads work from the Foundation.
* The interrupt-enable stack discipline has been simplified.
* An optional mechanism to change the base ISA used by supervisor and
user modes has been added to the `mstatus` CSR, and the field previously
-called Base in `misa` has been renamed to ` MXL` for consistency.
+called Base in `misa` has been renamed to `MXL` for consistency.
* Clarified expected use of XS to summarize additional extension state
status fields in `mstatus`.
* Optional vectored interrupt support has been added to the `mtvec` and