Added clearer definitions of execution environments and harts.

1 files changed, 0 insertions, 41 deletions

diff --git a/src/priv-intro.tex b/src/priv-intro.tex
index 26ab433..bf30b32 100644
--- a/src/priv-intro.tex
+++ b/src/priv-intro.tex
@@ -26,47 +26,6 @@ protection model.  Alternate privileged specifications could embody
 other more flexible protection-domain models.
 \end{commentary}
 
-\section{RISC-V Hardware Platform Terminology}
-
-A RISC-V hardware platform can contain one or more RISC-V-compatible
-processing cores together with other non-RISC-V-compatible cores,
-fixed-function accelerators, various physical memory structures, I/O
-devices, and an interconnect structure to allow the components to
-communicate.
-
-A component is termed a {\em core} if it contains an independent
-instruction fetch unit.  A RISC-V-compatible core might support
-multiple RISC-V-compatible hardware threads, or {\em harts}, through
-multithreading.
-
-A RISC-V core might have additional specialized instruction set
-extensions or an added {\em coprocessor}.  We use the term {\em
-  coprocessor} to refer to a unit that is attached to a RISC-V core
-and is mostly sequenced by a RISC-V instruction stream, but which
-contains additional architectural state and instruction set
-extensions, and possibly some limited autonomy relative to the
-primary RISC-V instruction stream.
-
-We use the term {\em accelerator} to refer to either a
-non-programmable fixed-function unit or a core that can operate
-autonomously but is specialized for certain tasks.  In RISC-V systems,
-we expect many programmable accelerators will be RISC-V-based cores
-with specialized instruction set extensions and/or customized
-coprocessors.  An important class of RISC-V accelerators are I/O
-accelerators, which offload I/O processing tasks from the main
-application cores.
-
-The system-level organization of a RISC-V hardware platform can range
-from a single-core microcontroller to a many-thousand-node cluster of
-shared-memory manycore server nodes.  Even small systems-on-a-chip
-might be structured as a hierarchy of multicomputers and/or
-multiprocessors to modularize development effort or to provide secure
-isolation between subsystems.
-
-This document focuses on the privileged architecture visible to each
-hart (hardware thread) running within a uniprocessor or a
-shared-memory multiprocessor.
-
 \section{RISC-V Privileged Software Stack Terminology}
 
 This section describes the terminology we use to describe components