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| author | Andrew Waterman <andrew@sifive.com> | 2017-06-24 23:54:24 -0700 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2017-06-24 23:54:24 -0700 |
| commit | 6b9e06265c304b4b18c92ce241cbc196f3f37fc6 (patch) | |
| tree | b3724ba3e1b7ecbf21aa59ed4ee800a6c963a974 /src/priv-intro.tex | |
| parent | 7c12718366391354e11f2a3df98c7543c22661c8 (diff) | |
| download | riscv-isa-manual-6b9e06265c304b4b18c92ce241cbc196f3f37fc6.zip riscv-isa-manual-6b9e06265c304b4b18c92ce241cbc196f3f37fc6.tar.gz riscv-isa-manual-6b9e06265c304b4b18c92ce241cbc196f3f37fc6.tar.bz2 | |
Fix typo
Diffstat (limited to 'src/priv-intro.tex')
| -rw-r--r-- | src/priv-intro.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-intro.tex b/src/priv-intro.tex index ca1ea41..26ab433 100644 --- a/src/priv-intro.tex +++ b/src/priv-intro.tex @@ -180,7 +180,7 @@ focusing on hypervisor support via an extended S mode suitable for both Type-1 and Type-2 hypervisors as described in Chapter~\ref{hypervisor}. The encoding space for H is reserved for future use and to avoid backwards incompatible changes in bit -positions in various status regusters. The bit positions might be +positions in various status registers. The bit positions might be reused in the future for different Type-1 hypervisor support or possibly additional secure execution modes. \end{commentary} |