diff options
| author | Andrew Waterman <andrew@sifive.com> | 2021-09-08 17:54:37 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-08 17:54:37 -0700 |
| commit | 5a141642f7bf36ed0d2085de0ecc66ffbb41d909 (patch) | |
| tree | 49eb372072d9e1e8d838fcf13c64f341043e011a /src/priv-csrs.tex | |
| parent | 0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2 (diff) | |
| parent | 5e685a6f166cbcf6790491681e2d8ad5c3788d9a (diff) | |
| download | riscv-isa-manual-5a141642f7bf36ed0d2085de0ecc66ffbb41d909.zip riscv-isa-manual-5a141642f7bf36ed0d2085de0ecc66ffbb41d909.tar.gz riscv-isa-manual-5a141642f7bf36ed0d2085de0ecc66ffbb41d909.tar.bz2 | |
Merge pull request #727 from riscv/mseccfg
Add mseccfg and *envcfg CSRs
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 9cff6d6..99db7ce 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -197,6 +197,10 @@ Number & Privilege & Name & Description \\ \tt 0x105 & SRW &\tt stvec & Supervisor trap handler base address. \\ \tt 0x106 & SRW &\tt scounteren & Supervisor counter enable. \\ \hline +\multicolumn{4}{|c|}{Supervisor Configuration} \\ +\hline +\tt 0x10A & MRW &\tt senvcfg & Supervisor environment configuration register. \\ +\hline \multicolumn{4}{|c|}{Supervisor Trap Handling} \\ \hline \tt 0x140 & SRW &\tt sscratch & Scratch register for supervisor trap handlers. \\ @@ -243,6 +247,11 @@ Number & Privilege & Name & Description \\ \tt 0x64A & HRW &\tt htinst & Hypervisor trap instruction (transformed). \\ \tt 0xE12 & HRO &\tt hgeip & Hypervisor guest external interrupt pending. \\ \hline +\multicolumn{4}{|c|}{Hypervisor Configuration} \\ +\hline +\tt 0x60A & MRW &\tt henvcfg & Hypervisor environment configuration register. \\ +\tt 0x61A & MRW &\tt henvcfgh & Additional hypervisor env. conf. register, RV32 only. \\ +\hline \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ \hline \tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ @@ -310,6 +319,13 @@ Number & Privilege & Name & Description \\ \tt 0x34A & MRW &\tt mtinst & Machine trap instruction (transformed). \\ \tt 0x34B & MRW &\tt mtval2 & Machine bad guest physical address. \\ \hline +\multicolumn{4}{|c|}{Machine Configuration} \\ +\hline +\tt 0x30A & MRW &\tt menvcfg & Machine environment configuration register. \\ +\tt 0x31A & MRW &\tt menvcfgh & Additional machine env. conf. register, RV32 only. \\ +\tt 0x747 & MRW &\tt mseccfg & Machine security configuration register. \\ +\tt 0x757 & MRW &\tt mseccfgh & Additional machine security conf. register, RV32 only. \\ +\hline \multicolumn{4}{|c|}{Machine Memory Protection} \\ \hline %\tt 0x380 & MRW &\tt mbase & Base register. \\ |