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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-09-05 17:36:43 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-05 17:36:43 -0700 |
| commit | 0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2 (patch) | |
| tree | b0cb9548340582f6e7821029212b40b301af6b09 /src/priv-csrs.tex | |
| parent | 5bce9789a9183f553ca444d820e9152bde442c54 (diff) | |
| download | riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.zip riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.tar.gz riscv-isa-manual-0abcad44c0b63e8f8aaf6d8f2dfac923f4312cb2.tar.bz2 | |
Make virtual instruction exceptions more consistent for VU mode (#730)
Raise a virtual instruction exception when V = 1 if an attempted
instruction is HS-qualified but is explicitly blocked by either a
hypervisor CSR or a supervisor CSR. Previously, the document was
inconsistent whether an illegal instruction or virtual instruction
exception is raised when an instruction is blocked from executing in
VU mode solely by a supervisor CSR such as scounteren.
Diffstat (limited to 'src/priv-csrs.tex')
0 files changed, 0 insertions, 0 deletions