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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-21 03:15:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-21 03:33:31 -0800 |
| commit | 9ffebdbb329d43893d62df5af47ae1a4602a18cc (patch) | |
| tree | 2aa183025a0619b164c83460f70f1a8b209358f2 /src/priv-csrs.tex | |
| parent | 786d9b896c0b00b9665b28b39c0698ee7bde54bf (diff) | |
| download | riscv-isa-manual-9ffebdbb329d43893d62df5af47ae1a4602a18cc.zip riscv-isa-manual-9ffebdbb329d43893d62df5af47ae1a4602a18cc.tar.gz riscv-isa-manual-9ffebdbb329d43893d62df5af47ae1a4602a18cc.tar.bz2 | |
Add counter-inhibit mechanism
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 1f723a9..239a4f9 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -336,6 +336,7 @@ Number & Privilege & Name & Description \\ \hline \multicolumn{4}{|c|}{Machine Counter Setup} \\ \hline +\tt 0x320 & MRW &\tt mcountinhibit & Machine counter-inhibit register. \\ \tt 0x323 & MRW &\tt mhpmevent3 & Machine performance-monitoring event selector. \\ \tt 0x324 & MRW &\tt mhpmevent4 & Machine performance-monitoring event selector. \\ & & \multicolumn{1}{c|}{\vdots} & \ \\ |