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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-26 09:00:32 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-26 09:00:32 -0700 |
| commit | 7ad0e995f215997b68437010fce36f401d515dbc (patch) | |
| tree | 029083ebe8ea1fd977ef8d1fb93d9af862adf4ac /src/priv-csrs.tex | |
| parent | a2a3346e7345619efe3b5e8620d4a87c72d21ad0 (diff) | |
| download | riscv-isa-manual-7ad0e995f215997b68437010fce36f401d515dbc.zip riscv-isa-manual-7ad0e995f215997b68437010fce36f401d515dbc.tar.gz riscv-isa-manual-7ad0e995f215997b68437010fce36f401d515dbc.tar.bz2 | |
Replaced mbadaddr with mbadbits register, which can now capture bad
instruction bits on an illegal instruction fault.
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index fe0bce2..02298e4 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -159,7 +159,7 @@ Number & Privilege & Name & Description \\ \tt 0x040 & URW &\tt uscratch & Scratch register for user trap handlers. \\ \tt 0x041 & URW &\tt uepc & User exception program counter. \\ \tt 0x042 & URW &\tt ucause & User trap cause. \\ -\tt 0x043 & URW &\tt ubadaddr & User bad address. \\ +\tt 0x043 & URW &\tt ubadbits & User bad address or instruction. \\ \tt 0x044 & URW &\tt uip & User interrupt pending. \\ \hline \multicolumn{4}{|c|}{User Floating-Point CSRs} \\ @@ -212,7 +212,7 @@ Number & Privilege & Name & Description \\ \tt 0x140 & SRW &\tt sscratch & Scratch register for supervisor trap handlers. \\ \tt 0x141 & SRW &\tt sepc & Supervisor exception program counter. \\ \tt 0x142 & SRW &\tt scause & Supervisor trap cause. \\ -\tt 0x143 & SRW &\tt sbadaddr & Supervisor bad address. \\ +\tt 0x143 & SRW &\tt sbadbits & Supervisor bad address. \\ \tt 0x144 & SRW &\tt sip & Supervisor interrupt pending. \\ \hline \multicolumn{4}{|c|}{Supervisor Protection and Translation} \\ @@ -245,7 +245,7 @@ Number & Privilege & Name & Description \\ %% \tt 0x240 & HRW &\tt hscratch & Scratch register for hypervisor trap handlers. \\ %% \tt 0x241 & HRW &\tt hepc & Hypervisor exception program counter. \\ %% \tt 0x242 & HRW &\tt hcause & Hypervisor trap cause. \\ -%% \tt 0x243 & HRW &\tt hbadaddr & Hypervisor bad address. \\ +%% \tt 0x243 & HRW &\tt hbadbits & Hypervisor bad address or instruction. \\ %% \tt 0x244 & HRW &\tt hip & Hypervisor interrupt pending. \\ %% \hline %% \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ @@ -287,7 +287,7 @@ Number & Privilege & Name & Description \\ \tt 0x340 & MRW &\tt mscratch & Scratch register for machine trap handlers. \\ \tt 0x341 & MRW &\tt mepc & Machine exception program counter. \\ \tt 0x342 & MRW &\tt mcause & Machine trap cause. \\ -\tt 0x343 & MRW &\tt mbadaddr & Machine bad address. \\ +\tt 0x343 & MRW &\tt mbadbits & Machine bad address or instruction. \\ \tt 0x344 & MRW &\tt mip & Machine interrupt pending. \\ \hline \multicolumn{4}{|c|}{Machine Protection and Translation} \\ |