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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-06 11:36:46 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-06 11:36:46 -0800 |
| commit | 738c4d7735a6f15d65ef6ab91d728eb86f425722 (patch) | |
| tree | 8053848e16c7d152695fedb84b8a8a4cc47d63f4 /src/priv-csrs.tex | |
| parent | a7cf36df81cf938919eede162c7ff0fc88b28e91 (diff) | |
| download | riscv-isa-manual-738c4d7735a6f15d65ef6ab91d728eb86f425722.zip riscv-isa-manual-738c4d7735a6f15d65ef6ab91d728eb86f425722.tar.gz riscv-isa-manual-738c4d7735a6f15d65ef6ab91d728eb86f425722.tar.bz2 | |
Hypervisor tweaks
h/t JohnH
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 03164cd..c00629a 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -302,8 +302,8 @@ Number & Privilege & Name & Description \\ \tt 0x342 & MRW &\tt mcause & Machine trap cause. \\ \tt 0x343 & MRW &\tt mtval & Machine bad address or instruction. \\ \tt 0x344 & MRW &\tt mip & Machine interrupt pending. \\ -\tt 0x34A & HRW &\tt mtinst & Machine trap instruction (transformed). \\ -\tt 0x34B & HRW &\tt mtval2 & Machine bad guest physical address. \\ +\tt 0x34A & MRW &\tt mtinst & Machine trap instruction (transformed). \\ +\tt 0x34B & MRW &\tt mtval2 & Machine bad guest physical address. \\ \hline \multicolumn{4}{|c|}{Machine Memory Protection} \\ \hline |