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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-19 17:43:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-19 21:12:07 -0700 |
| commit | 2151617320bc7d27d3ce8415be306ab51c362508 (patch) | |
| tree | 836e16eda65fa62ef60fdc1ce7258259a6b152a5 /src/priv-csrs.tex | |
| parent | 6568b54f83d8a1c390f2f47a29b294d2f9ba270d (diff) | |
| download | riscv-isa-manual-2151617320bc7d27d3ce8415be306ab51c362508.zip riscv-isa-manual-2151617320bc7d27d3ce8415be306ab51c362508.tar.gz riscv-isa-manual-2151617320bc7d27d3ce8415be306ab51c362508.tar.bz2 | |
Add endianness control proposal to priv spec
Contributed by @jhauser-us
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 445a2b7..dad890b 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -281,6 +281,7 @@ Number & Privilege & Name & Description \\ \tt 0x304 & MRW &\tt mie & Machine interrupt-enable register. \\ \tt 0x305 & MRW &\tt mtvec & Machine trap-handler base address. \\ \tt 0x306 & MRW &\tt mcounteren & Machine counter enable. \\ +\tt 0x310 & MRW &\tt mstatush & Additional machine status register, RV32 only. \\ \hline \multicolumn{4}{|c|}{Machine Trap Handling} \\ \hline |