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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-19 20:06:32 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-19 20:06:32 -0700 |
| commit | 14f269d349d4e0f211752b3217bf7958ed6fc5d2 (patch) | |
| tree | 43593eb2ef45bfdb67bea62b82f194225642e472 /src/priv-csrs.tex | |
| parent | 66ca5c0d95686839f3c7e41d7cfe7428b7dc8693 (diff) | |
| download | riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.zip riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.tar.gz riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.tar.bz2 | |
Excised H-mode from spec.
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 83 |
1 files changed, 43 insertions, 40 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 2e0f198..48b7ac2 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -64,15 +64,18 @@ less-privileged software. \tt 11 &\tt 01 &\tt 00-10 & \tt 0xD00-0xDBF & Standard read-only \\ \tt 11 &\tt 01 &\tt 11 & \tt 0xDC0-0xDFF & Non-standard read-only \\ \hline -\multicolumn{5}{|c|}{Hypervisor CSRs} \\ +\multicolumn{5}{|c|}{Reserved CSRs} \\ \hline -\tt 00 &\tt 10 &\tt XX & \tt 0x200-0x2FF & Standard read/write \\ -\tt 01 &\tt 10 &\tt 00-10 & \tt 0x600-0x6BF & Standard read/write \\ -\tt 01 &\tt 10 &\tt 11 & \tt 0x6C0-0x6FF & Non-standard read/write \\ -\tt 10 &\tt 10 &\tt 00-10 & \tt 0xA00-0xABF & Standard read/write shadows \\ -\tt 10 &\tt 10 &\tt 11 & \tt 0xAC0-0xAFF & Non-standard read/write shadows \\ -\tt 11 &\tt 10 &\tt 00-10 & \tt 0xE00-0xEBF & Standard read-only \\ -\tt 11 &\tt 10 &\tt 11 & \tt 0xEC0-0xEFF & Non-standard read-only \\ +\tt XX &\tt 10 &\tt XX & Reserved & \\ +%% \multicolumn{5}{|c|}{Hypervisor CSRs} \\ +%% \hline +%% \tt 00 &\tt 10 &\tt XX & \tt 0x200-0x2FF & Standard read/write \\ +%% \tt 01 &\tt 10 &\tt 00-10 & \tt 0x600-0x6BF & Standard read/write \\ +%% \tt 01 &\tt 10 &\tt 11 & \tt 0x6C0-0x6FF & Non-standard read/write \\ +%% \tt 10 &\tt 10 &\tt 00-10 & \tt 0xA00-0xABF & Standard read/write shadows \\ +%% \tt 10 &\tt 10 &\tt 11 & \tt 0xAC0-0xAFF & Non-standard read/write shadows \\ +%% \tt 11 &\tt 10 &\tt 00-10 & \tt 0xE00-0xEBF & Standard read-only \\ +%% \tt 11 &\tt 10 &\tt 11 & \tt 0xEC0-0xEFF & Non-standard read-only \\ \hline \multicolumn{5}{|c|}{Machine CSRs} \\ \hline @@ -215,38 +218,38 @@ Number & Privilege & Name & Description \\ \label{scsrnames} \end{table} -\begin{table}[htb!] -\begin{center} -\begin{tabular}{|l|l|l|l|} -\hline -Number & Privilege & Name & Description \\ -\hline -\multicolumn{4}{|c|}{Hypervisor Trap Setup} \\ -\hline -\tt 0x200 & HRW &\tt hstatus & Hypervisor status register. \\ -\tt 0x202 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ -\tt 0x203 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ -\tt 0x204 & HRW &\tt hie & Hypervisor interrupt-enable register. \\ -\tt 0x205 & HRW &\tt htvec & Hypervisor trap handler base address. \\ -\tt 0x206 & HRW &\tt hcounteren & Hypervisor counter enable. \\ -\hline -\multicolumn{4}{|c|}{Hypervisor Trap Handling} \\ -\hline -\tt 0x240 & HRW &\tt hscratch & Scratch register for hypervisor trap handlers. \\ -\tt 0x241 & HRW &\tt hepc & Hypervisor exception program counter. \\ -\tt 0x242 & HRW &\tt hcause & Hypervisor trap cause. \\ -\tt 0x243 & HRW &\tt hbadaddr & Hypervisor bad address. \\ -\tt 0x244 & HRW &\tt hip & Hypervisor interrupt pending. \\ -\hline -\multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ -\hline -\tt 0x28X & TBD & TBD & TBD. \\ -\hline -\end{tabular} -\end{center} -\caption{Currently allocated RISC-V hypervisor-level CSR addresses.} -\label{hcsrnames} -\end{table} +%% \begin{table}[htb!] +%% \begin{center} +%% \begin{tabular}{|l|l|l|l|} +%% \hline +%% Number & Privilege & Name & Description \\ +%% \hline +%% \multicolumn{4}{|c|}{Hypervisor Trap Setup} \\ +%% \hline +%% \tt 0x200 & HRW &\tt hstatus & Hypervisor status register. \\ +%% \tt 0x202 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ +%% \tt 0x203 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ +%% \tt 0x204 & HRW &\tt hie & Hypervisor interrupt-enable register. \\ +%% \tt 0x205 & HRW &\tt htvec & Hypervisor trap handler base address. \\ +%% \tt 0x206 & HRW &\tt hcounteren & Hypervisor counter enable. \\ +%% \hline +%% \multicolumn{4}{|c|}{Hypervisor Trap Handling} \\ +%% \hline +%% \tt 0x240 & HRW &\tt hscratch & Scratch register for hypervisor trap handlers. \\ +%% \tt 0x241 & HRW &\tt hepc & Hypervisor exception program counter. \\ +%% \tt 0x242 & HRW &\tt hcause & Hypervisor trap cause. \\ +%% \tt 0x243 & HRW &\tt hbadaddr & Hypervisor bad address. \\ +%% \tt 0x244 & HRW &\tt hip & Hypervisor interrupt pending. \\ +%% \hline +%% \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ +%% \hline +%% \tt 0x28X & TBD & TBD & TBD. \\ +%% \hline +%% \end{tabular} +%% \end{center} +%% \caption{Currently allocated RISC-V hypervisor-level CSR addresses.} +%% \label{hcsrnames} +%% \end{table} \begin{table}[htb!] |