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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-07 23:01:00 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-07 23:01:00 -0700 |
| commit | 627495d8a6935b03f3c09164f27a67393ef3173d (patch) | |
| tree | af5a1bbb8ce1440ff3e7426d84fe779b984fa59d /src/preface.tex | |
| parent | 22a0383af387e761b52f521a63c6e45f7fff7f74 (diff) | |
| download | riscv-isa-manual-627495d8a6935b03f3c09164f27a67393ef3173d.zip riscv-isa-manual-627495d8a6935b03f3c09164f27a67393ef3173d.tar.gz riscv-isa-manual-627495d8a6935b03f3c09164f27a67393ef3173d.tar.bz2 | |
Broke out actual perf counters into separate chapter.
Diffstat (limited to 'src/preface.tex')
| -rw-r--r-- | src/preface.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/preface.tex b/src/preface.tex index ad1681d..06cb435 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -67,7 +67,7 @@ The major changes in this version of the document include: produced illegal instruction exceptions in RV32E and RV64I chapters. \item Counter/timer instructions are now not considered part of mandatory base ISA, and so CSR instructions were moved into separate - chapter. + chapter, with the unprivileged counters into another separate chapter. \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, and changed their behavior on signaling-NaN inputs to conform to the minimumNumber and maximumNumber operations in the proposed IEEE 754-201x |