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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 04:10:17 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 04:10:17 -0700 |
| commit | 76f3c072674a3a3b0eeefe767ca1b52107998c8d (patch) | |
| tree | 4f82486277de06f223a59bdc72d33889d0f80be4 /src/plic.tex | |
| parent | 727914cc3d553851dbf572a2aff52aa4ef0b7841 (diff) | |
| download | riscv-isa-manual-76f3c072674a3a3b0eeefe767ca1b52107998c8d.zip riscv-isa-manual-76f3c072674a3a3b0eeefe767ca1b52107998c8d.tar.gz riscv-isa-manual-76f3c072674a3a3b0eeefe767ca1b52107998c8d.tar.bz2 | |
Removed explicit convention on shadow CSRs.
Diffstat (limited to 'src/plic.tex')
| -rw-r--r-- | src/plic.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/plic.tex b/src/plic.tex index 3319506..fcf366d 100644 --- a/src/plic.tex +++ b/src/plic.tex @@ -99,7 +99,7 @@ support delegating external interrupts to lower-privilege modes, then the lower-privilege hart contexts will not be interrupt targets. Interrupt notifications generated by the PLIC appear in the {\tt meip}/{\tt seip}/{\tt ueip} bits of the {\tt mip}/{\tt sip}/{\tt - uip} registers for M/H/S/U modes respectively. The notifications + uip} registers for M/S/U modes respectively. The notifications only appear in lower-privilege {\em x}{\tt ip} registers if external interrupts have been delegated to the lower-privilege modes. |