Excised H-mode from spec.

1 files changed, 7 insertions, 8 deletions

diff --git a/src/plic.tex b/src/plic.tex
index 798b139..3319506 100644
--- a/src/plic.tex
+++ b/src/plic.tex
@@ -98,11 +98,10 @@ be interrupt targets, in particular, if a processor core does not
 support delegating external interrupts to lower-privilege modes, then
 the lower-privilege hart contexts will not be interrupt targets.
 Interrupt notifications generated by the PLIC appear in the {\tt
-  meip}/{\tt heip}/{\tt seip}/{\tt ueip} bits of the {\tt mip}/{\tt
-  hip}/{\tt sip}/{\tt uip} registers for M/H/S/U modes respectively.
-The notifications only appear in lower-privilege {\em x}{\tt ip}
-registers if external interrupts have been delegated to the
-lower-privilege modes.
+  meip}/{\tt seip}/{\tt ueip} bits of the {\tt mip}/{\tt sip}/{\tt
+  uip} registers for M/H/S/U modes respectively.  The notifications
+only appear in lower-privilege {\em x}{\tt ip} registers if external
+interrupts have been delegated to the lower-privilege modes.
 
 Each processor core must define a policy on how simultaneous active
 interrupts are taken by multiple hart contexts on the core. For the
@@ -266,7 +265,7 @@ interrupt sources, interrupt targets, or other agents manipulating
 register values in the PLIC.  The value in EIP is communicated to the
 destination target as an interrupt notification.  If the target is a
 RISC-V hart context, the interrupt notifications arrive on the {\tt
-  meip}/{\tt heip}/{\tt seip}/{\tt ueip} bits depending on the
+  meip}/{\tt seip}/{\tt ueip} bits depending on the
 privilege level of the hart context.
 
 \begin{commentary}
@@ -321,7 +320,7 @@ After the highest-priority pending interrupt is claimed by a target
 and the corresponding IP bit is cleared, other lower-priority pending
 interrupts might then become visible to the target, and so the PLIC
 EIP bit might not be cleared after a claim.  The interrupt handler
-can check the local {\tt meip}/{\tt heip}/{\tt seip}/{\tt ueip} bits
+can check the local {\tt meip}/{\tt seip}/{\tt ueip} bits
 before exiting the handler, to allow more efficient service of other
 interrupts without first restoring the interrupted context and taking
 another interrupt trap.
@@ -414,7 +413,7 @@ each action over many clock cycles.
 In the expected use case, only machine mode accesses the source
 priority, source pending, and target interrupt enables to configure
 the interrupt subsystem.  Lower-privilege modes access these features
-via ABI, SBI, or HBI calls. The interrupt enables act as a protection
+via ABI or SBI calls. The interrupt enables act as a protection
 mechanism where a target can only signal completion to an interrupt
 gateway that is currently enabled for that target.