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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-02 19:29:09 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-02 19:29:09 -0800 |
| commit | 296fad700431eaa525ab83b8d6c30dfcd9509661 (patch) | |
| tree | c3662627d07202ad246c03c4afafb7324309a8d5 /src/plic.tex | |
| parent | 9c6ddaf4382f610a1161173e5a993cb9c2c298bb (diff) | |
| download | riscv-isa-manual-296fad700431eaa525ab83b8d6c30dfcd9509661.zip riscv-isa-manual-296fad700431eaa525ab83b8d6c30dfcd9509661.tar.gz riscv-isa-manual-296fad700431eaa525ab83b8d6c30dfcd9509661.tar.bz2 | |
Non-standard -> custom
Diffstat (limited to 'src/plic.tex')
| -rw-r--r-- | src/plic.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/plic.tex b/src/plic.tex index f976e49..48e53de 100644 --- a/src/plic.tex +++ b/src/plic.tex @@ -67,13 +67,13 @@ handler must clear the hardware condition that is causing the {\tt mip} bit to be set to avoid retaking the interrupt after re-enabling interrupts on exit from the interrupt handler. -Additional non-standard local interrupt sources can be made visible to +Additional platform-specific local interrupt sources can be made visible to machine-mode by adding them to the high bits of the {\tt mip}/{\tt mie} registers, with corresponding additional cause values returned -in the {\tt mcause} register. These additional non-standard local +in the {\tt mcause} register. These additional platform-specific local interrupts may also be made visible to lower privilege levels, using the corresponding bits in the {\tt mideleg} register. The priority of -non-standard local interrupt sources relative to external, timer, and +these additional interrupt sources relative to external, timer, and software interrupts is platform-specific. \subsection{Global Interrupt Sources} |