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authorAndrew Waterman <andrew@sifive.com>2018-12-20 15:51:19 -0800
committerAndrew Waterman <andrew@sifive.com>2018-12-20 15:53:33 -0800
commita7826272c6bcfdcd74acf05b38bb28e46594190a (patch)
treeb9a340e456c66a0fa2150632ebb5e7548ed31b6e /src/naming.tex
parent9c98df74ee8bddbbdd0d1f09c8cc8b99d526b274 (diff)
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Clean up naming and define G = IMAFDZicsr_Zifencei
Closes #266.
Diffstat (limited to 'src/naming.tex')
-rw-r--r--src/naming.tex30
1 files changed, 14 insertions, 16 deletions
diff --git a/src/naming.tex b/src/naming.tex
index f3e9ed0..661e50f 100644
--- a/src/naming.tex
+++ b/src/naming.tex
@@ -35,7 +35,7 @@ Any RISC-V instruction-set variant can be succinctly described by
concatenating the base integer prefix with the names of the included
extensions, e.g., ``RV64IMAFD''.
-We have also defined an abbreviation ``G'' to represent the ``IMAFD''
+We have also defined an abbreviation ``G'' to represent the ``IMAFDZicsr\_Zifencei''
base and extensions, as this is intended to represent our standard
general-purpose ISA.
@@ -58,15 +58,11 @@ loss of backwards compatibility, whereas changes in only the minor
version number must be backwards-compatible. For example, the
original 64-bit standard ISA defined in release 1.0 of this manual can
be written in full as ``RV64I1p0M1p0A1p0F1p0D1p0'', more concisely as
-``RV64I1M1A1F1D1'', or even more concisely as ``RV64G1''. The G ISA
-can be written as ``RV64I2p0M2p0A2p0F2p0D2p0'', or more
-concisely ``RV64G2''.
+``RV64I1M1A1F1D1''.
-We introduced the version numbering scheme with the second release,
-which we also intend to become a permanent standard. Hence, we define
-the default version of a standard extension to be that present at the
-time of this document, e.g., ``RV32G'' is equivalent to
-``RV32I2M2A2F2D2''.
+We introduced the version numbering scheme with the second release. Hence, we
+define the default version of a standard extension to be the version present at that
+time, e.g., ``RV32I'' is equivalent to ``RV32I2''.
\section{Underscores}
@@ -88,7 +84,7 @@ Chapter~\ref{chap:zifencei}; ``Zifencei2'' and ``Zifencei2p0'' name version
Extensions with the ``Z'' prefix must be separated
from other multi-letter extensions by an underscore, e.g.,
-``RV32IMACZifencei\_Zicsr''.
+``RV32IMACZicsr\_Zifencei''.
\section{Non-Standard Extension Names}
@@ -102,16 +98,14 @@ by an underscore. For example, an ISA with non-standard extensions
Argle and Bargle may be named ``RV64IZifencei\_Xargle\_Xbargle''.
\section{Supervisor-level Instruction-Set Extensions}
+
Standard supervisor instruction-set extensions are defined in Volume II, but
are named using ``S'' as a prefix, followed by an
alphabetical name and an optional version number.
-
-Supervisor extensions must be separated from other multi-letter extensions
-by an underscore.
-
-\section{Supervisor-level Extensions}
Non-standard extensions to the supervisor-level ISA are defined using
the ``SX'' prefix.
+Supervisor extensions must be separated from other multi-letter extensions
+by an underscore.
\section{Subset Naming Convention}
Table~\ref{isanametable} summarizes the standardized extension names.
@@ -130,8 +124,10 @@ Integer Multiplication and Division & M \\
Atomics & A \\
Single-Precision Floating-Point & F \\
Double-Precision Floating-Point & D \\
+Control and Status Register Access & Zicsr \\
+Instruction-Fetch Fence & Zifencei \\
\hline
-General & G = IMAFD \\
+General & G = IMAFDZicsr\_Zifencei \\
\hline
\multicolumn{2}{|c|}{Standard Unprivileged Extensions}\\
\hline
@@ -144,6 +140,8 @@ Transactional Memory & T \\
Packed-SIMD Extensions & P \\
Vector Extensions & V \\
User-Level Interrupts & N \\
+Misaligned Atomics & Zam \\
+Total Store Ordering & Ztso \\
\hline
\hline
\multicolumn{2}{|c|}{Non-Standard Unprivileged Extensions}\\