Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual into tymcauley-misc-fixes

1 files changed, 1 insertions, 1 deletions

diff --git a/src/memory.tex b/src/memory.tex
index fcaa9c6..619bd38 100644
--- a/src/memory.tex
+++ b/src/memory.tex
@@ -889,7 +889,7 @@ The ordering guarantees in this section may not apply beyond a platform-specific
 Table~\ref{tab:tsomappings} provides a mapping from TSO memory operations onto RISC-V memory instructions.
 Normal x86 loads and stores are all inherently acquire-RCpc and release-RCpc operations: TSO enforces all load-load, load-store, and store-store ordering by default.
 Therefore, under RVWMO, all TSO loads must be mapped onto a load followed by FENCE~R,RW, and all TSO stores must be mapped onto FENCE~RW,W followed by a store.
-TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully-ordered and can be implemented either via an AMO with both {\em aq} and {\em rl} set, or via an LR with {\em aq} set, the aritmentic operation in question, an SC with both {\em aq} and {\em rl} set, and a conditional branch checking the success condition.
+TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully-ordered and can be implemented either via an AMO with both {\em aq} and {\em rl} set, or via an LR with {\em aq} set, the arithmetic operation in question, an SC with both {\em aq} and {\em rl} set, and a conditional branch checking the success condition.
 In the latter case, the {\em rl} annotation on the LR turns out (for non-obvious reasons) to be redundant and can be omitted.
 
 Alternatives to Table~\ref{tab:tsomappings} are also possible.