Clarify interrupt delegation semantics (#158)

* Clarify interrupt delegation semantics

* Update contributors

1 files changed, 9 insertions, 2 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 8d717af..297c8bf 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1109,13 +1109,20 @@ then reading back the value in {\tt medeleg} or {\tt mideleg} to see
 which bit positions hold a one.
 
 Traps never transition from a more-privileged mode to a less-privileged mode.
-For example, if M-mode has delegated illegal instruction traps to S-mode, and
+For example, if M-mode has delegated illegal instruction exceptions to S-mode, and
 M-mode software later executes an illegal instruction, the trap is taken in
 M-mode, rather than being delegated to S-mode.  By contrast, traps may be
 taken horizontally.  Using the same example, if M-mode has delegated illegal
-instruction traps to S-mode, and S-mode software later executes an illegal
+instruction exceptions to S-mode, and S-mode software later executes an illegal
 instruction, the trap is taken in S-mode.
 
+Delegated interrupts result in the interrupt being masked at the delegator
+privilege level.  For example, if the supervisor timer interrupt (STI) is
+delegated to S-mode by setting {\tt mideleg}[5], STIs will not be taken when
+executing in M-mode.  By contrast, if {\tt mideleg}[5] is clear, STIs can
+be taken in any mode and regardless of current mode will transfer control to
+M-mode.
+
 \begin{figure}[h!]
 {\footnotesize
 \begin{center}