Hauser comments

1 files changed, 13 insertions, 15 deletions

diff --git a/src/machine.tex b/src/machine.tex
index e3d61bf..a002878 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -176,21 +176,19 @@ ISA observed at any level, and supports a much richer command
 interface without burdening hardware designs.
 \end{commentary}
 
-Unless {\tt misa} is hardwired to zero, the I and E bits are always
-complements of each other.  Hence, either both are read-only or both are
-writable.  If they are writable, then an attempt to set them to the same value
-{\em x} causes I to be set to {\em x} and E to be set to !{\em x}.
+The ``E'' bit is read-only.  Unless {\tt misa} is hardwired to zero, the ``E''
+bit always reads as the complement of the ``I'' bit.  An implementation that
+supports both RV32E and RV32I can select RV32E by clearing the ``I'' bit.
 
-The implementation may impose additional constraints on the collective setting
+If an ISA feature {\em x} depends on an ISA feature {\em y}, then attempting
+to enable feature {\em x} but disable feature {\em y} results in both features
+being disabled.  For example, setting ``F''=0 and ``D''=1 results in both
+``F'' and ``D'' being cleared.
+
+An implementation may impose additional constraints on the collective setting
 of two or more {\tt misa} fields, in which case they function collectively as
-a single \warl\ field.  For example, an implementation might require that the
-D bit be clear unless the F bit is set.  An attempt to write an unsupported
-combination causes those bits to be set to some supported combination.
-\begin{commentary}
-In the event that an unsupported combination is written to {\tt misa},
-it is recommended that the implementation select the supported combination
-with the fewest features enabled, to aid debugging of the error.
-\end{commentary}
+a single \warl\ field.  An attempt to write an unsupported combination causes
+those bits to be set to some supported combination.
 
 Writing {\tt misa} may increase IALIGN, e.g., by disabling the ``C''
 extension.
@@ -715,8 +713,8 @@ hooks necessary to lazily populate shadow page tables.
 \end{commentary}
 
 The TW (Timeout Wait) bit supports intercepting the WFI instruction (see
-Section~\ref{wfi}).  When TW=0, the TW mechanism does not inhibit the WFI
-instruction from executing in the next-lowest privileged mode.  When TW=1,
+Section~\ref{wfi}).  When TW=0, the WFI instruction may execute in lower
+privilege modes when not prevented for some other reason.  When TW=1,
 then if WFI is executed in any less-privileged mode, and it does not complete
 within an implementation-specific, bounded time limit, the WFI instruction
 causes an illegal instruction exception.  The time limit may always be 0, in which