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| author | Andrew Waterman <andrew@sifive.com> | 2017-10-20 11:34:28 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-10-20 11:34:28 -0700 |
| commit | d420a9a5123e03b2d6fb652a9c4e8ad8700a40a3 (patch) | |
| tree | af4efb1175cb9b4d9f27226016b5df6d698b1ca4 /src/machine.tex | |
| parent | e22b943f7a7826072620de9be269243e758cc58c (diff) | |
| download | riscv-isa-manual-d420a9a5123e03b2d6fb652a9c4e8ad8700a40a3.zip riscv-isa-manual-d420a9a5123e03b2d6fb652a9c4e8ad8700a40a3.tar.gz riscv-isa-manual-d420a9a5123e03b2d6fb652a9c4e8ad8700a40a3.tar.bz2 | |
Put the onus on software to align pc/epc when clearing misa.C
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 9960a4c..19f5988 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -171,6 +171,9 @@ ISA observed at any level, and supports a much richer command interface without burdening hardware designs. \end{commentary} +When clearing the ``C'' bit in {\tt misa}, software must ensure that the +current {\tt pc} is 4-byte aligned and that all {\em x}{\tt epc} registers +contain 4-byte-aligned values. \clearpage |