diff options
author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-15 09:25:28 -0700 |
---|---|---|
committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-15 09:25:28 -0700 |
commit | c906097f61ccc2ede211286eae4af387a3b2ea79 (patch) | |
tree | 7366e591ab291691dc7470458f52b32c39533500 /src/machine.tex | |
parent | 1618242dfd5445b6e1d4fcab3b67228c411277c3 (diff) | |
download | riscv-isa-manual-c906097f61ccc2ede211286eae4af387a3b2ea79.zip riscv-isa-manual-c906097f61ccc2ede211286eae4af387a3b2ea79.tar.gz riscv-isa-manual-c906097f61ccc2ede211286eae4af387a3b2ea79.tar.bz2 |
Reverting what would have been unintended change in spec. Interrupts
are considered globally enabled for privilege modes greater than the
current mode regardless of the setting of the global interrupt enable
for the higher privilege mode.
Diffstat (limited to 'src/machine.tex')
-rw-r--r-- | src/machine.tex | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/machine.tex b/src/machine.tex index 463dfee..5390879 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -509,30 +509,32 @@ ISAs respectively. \subsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} register} \label{privstack} -Interrupt-enable bits, MIE, SIE, and UIE, are provided for each +Global interrupt-enable bits, MIE, SIE, and UIE, are provided for each privilege mode. These bits are primarily used to guarantee atomicity with respect to interrupt handlers in the current privilege mode. \begin{commentary} -The {\em x}IE bits are located in the low-order bits of {\tt mstatus}, +The global {\em x}IE bits are located in the low-order bits of {\tt mstatus}, allowing them to be atomically set or cleared with a single CSR instruction. \end{commentary} When a hart is executing in privilege mode {\em x}, interrupts are -enabled when {\em x}\,IE=1. Interrupts for lower-privilege modes are -always disabled. Interrupts for higher-privilege modes can not be -disabled by lower-privilege modes. Higher-privilege-level code can -use separate per-interrupt enable bits to disable selected -high-privilege-mode interrupts before ceding control to a -lower-privilege mode. +globally enabled when {\em x}\,IE=1 and globally disabled when {\em + x}\,IE=0. Interrupts for lower-privilege modes, {\em w}$<${\em x}, +are always globally disabled regardless of the setting of the +lower-privilege mode's global {\em w}\,IE bit. Interrupts for +higher-privilege modes, {\em y}$>${\em x}, are always globally enabled +regardless of the setting of the higher-privilege mode's global {\em + y}\,IE bit. Higher-privilege-level code can use separate +per-interrupt enable bits to disable selected high-privilege-mode +interrupts before ceding control to a lower-privilege mode. \begin{commentary} A higher-privilege mode {\em y} could disable all of its interrupts - before ceding control to a lower-privilege mode by clearing {\em - y}\,IE but this would be unusual as it would leave only a synchronous - trap, non-maskable interrupt, or reset as means to regain control - of the hart. + before ceding control to a lower-privilege mode but this would be + unusual as it would leave only a synchronous trap, non-maskable + interrupt, or reset as means to regain control of the hart. \end{commentary} To support nested traps, each privilege mode {\em x} has a two-level |