Misc. address translation clarifications

Courtesy @gameboo in #205

1 files changed, 7 insertions, 7 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 1768a5c..8f7ab7e 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -638,13 +638,13 @@ widest supported width not wider than the new MXLEN.
 
 \subsection{Memory Privilege in {\tt mstatus} Register}
 
-The MPRV (Modify PRiVilege) bit modifies the privilege level at which
-loads and stores execute in all privilege modes.  When MPRV=0,
-translation and protection behave as normal.  When MPRV=1, load and
-store memory addresses are translated and protected as though the
-current privilege mode were set to MPP.  Instruction
-address-translation and protection are unaffected.  MPRV is hardwired
-to 0 if U-mode is not supported.
+The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads
+and stores execute in all privilege modes.  When MPRV=0, loads and stores
+behave as normal, using the translation and protection mechanisms of the
+current privilege mode.  When MPRV=1, load and store memory addresses are
+translated and protected as though the current privilege mode were set to MPP.
+Instruction address-translation and protection are unaffected by the setting
+of MPRV.  MPRV is hardwired to 0 if U-mode is not supported.
 
 The MXR (Make eXecutable Readable) bit modifies the privilege with which loads
 access virtual memory.  When MXR=0, only loads from pages marked readable (R=1