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| author | Alexandre Joannou <gameboo@users.noreply.github.com> | 2018-07-07 02:31:48 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-07-06 18:31:48 -0700 |
| commit | c4be3522f1494024364f9290e3e2df06cd69a9f7 (patch) | |
| tree | 3aa314fc88203f47218a94d74d6b33f19ea2ff2d /src/machine.tex | |
| parent | 7ea3f6755c483cba71eb59d052dc71bea139a5ce (diff) | |
| download | riscv-isa-manual-c4be3522f1494024364f9290e3e2df06cd69a9f7.zip riscv-isa-manual-c4be3522f1494024364f9290e3e2df06cd69a9f7.tar.gz riscv-isa-manual-c4be3522f1494024364f9290e3e2df06cd69a9f7.tar.bz2 | |
Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)
* Help the reader by pointing at TVM and TW in the relevant sections
* Mention TSR field in SRET description
* Avoid leaking M-mode details in S-mode text.
* Added a ref in SFENCE.VMA paragraph (PMP synchronization)
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 573441d..d8eeeb3 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -661,6 +661,7 @@ Note that, while SUM is ordinarily ignored when not executing in S-mode, it not supported. \subsection{Virtualization Support in {\tt mstatus} Register} +\label{virt-control} The TVM (Trap Virtual Memory) bit supports intercepting supervisor virtual-memory management operations. When TVM=1, @@ -2010,9 +2011,10 @@ MRET/SRET/URET & 0 & PRIV & 0 & SYSTEM \\ To return after handling a trap, there are separate trap return instructions per privilege level: MRET, SRET, and URET. MRET is always provided. SRET must be provided if supervisor mode is -supported, and should raise an illegal instruction otherwise. -URET is only provided if user-mode traps are supported, and -should raise an illegal instruction otherwise. +supported, and should raise an illegal instruction exception otherwise. SRET +should also raise an illegal instruction exception when TSR=1 in {\tt mstatus}, +as described in Section~\ref{virt-control}. URET is only provided if user-mode +traps are supported, and should raise an illegal instruction otherwise. An {\em x}\,RET instruction can be executed in privilege mode {\em x} or higher, where executing a lower-privilege {\em x}\,RET instruction will pop the relevant lower-privilege interrupt enable and privilege @@ -2038,7 +2040,9 @@ might need servicing. Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all of the supported S and M privilege modes, and optionally available to -U-mode for implementations that support U-mode interrupts. +U-mode for implementations that support U-mode interrupts. This instruction may +raise an illegal instruction exception when TW=1 in {\tt mstatus}, as described +in Section~\ref{virt-control}. \vspace{-0.2in} \begin{center} @@ -2920,6 +2924,7 @@ than XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is naturally aligned. \subsection{Physical Memory Protection and Paging} +\label{pmp-vmem} The Physical Memory Protection mechanism is designed to compose with the page-based virtual memory systems described in Chapter~\ref{supervisor}. When |