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| author | Andrew Waterman <andrew@sifive.com> | 2017-06-05 15:30:39 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-06-05 15:31:58 -0700 |
| commit | b901cdce8c24adef8713eb43dab6cc857e9ac041 (patch) | |
| tree | fad7b09112b28a1ae535d174f52bd0d42271d90d /src/machine.tex | |
| parent | cd20cee7efd9bac7c5aa127ec3b451749d2b3cce (diff) | |
| download | riscv-isa-manual-b901cdce8c24adef8713eb43dab6cc857e9ac041.zip riscv-isa-manual-b901cdce8c24adef8713eb43dab6cc857e9ac041.tar.gz riscv-isa-manual-b901cdce8c24adef8713eb43dab6cc857e9ac041.tar.bz2 | |
Reserve mip/mie bits below 16 for standard use
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/machine.tex b/src/machine.tex index 169956a..57becad 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1297,12 +1297,10 @@ interrupt-enable bits are hardwired to zero in the {\tt mip} and {\tt mie} registers respectively. Hence, these are all effectively \warl\ fields. -\begin{commentary} -Implementations can add additional platform-specific machine-level -interrupt sources to the high bits of these registers, though the -expectation is that most external interrupts will be routed through -the platform interrupt controller and be delivered via MEIP. -\end{commentary} +Implementations may add additional platform-specific machine-level +interrupt sources to bits 16 and above of the {\tt mip} and {\tt mie} +registers. The other unallocated interrupt sources (15--12, 10, 6, and 2) +are reserved for future standard use. An interrupt {\em i} will be taken if bit {\em i} is set in both {\tt mip} and {\tt mie}, and if interrupts are globally enabled. By |