diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-08-17 20:01:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-08-17 20:01:42 -0700 |
| commit | a62e76cb16eb508199f74632eb8bf263739f25a3 (patch) | |
| tree | bf0d558fe7ee15a3780a9debf3a60d3509c8dd90 /src/machine.tex | |
| parent | b6eea1464ff208d23e16b2f3638f312a7020a72b (diff) | |
| download | riscv-isa-manual-a62e76cb16eb508199f74632eb8bf263739f25a3.zip riscv-isa-manual-a62e76cb16eb508199f74632eb8bf263739f25a3.tar.gz riscv-isa-manual-a62e76cb16eb508199f74632eb8bf263739f25a3.tar.bz2 | |
Always order interrupt priority by privilege mode
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/_SECLWl8qWk
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index c7f5b14..efdedc9 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1316,8 +1316,8 @@ privilege mode is less than the delegated privilege mode. Multiple simultaneous interrupts destined for different privilege modes are handled in decreasing order of destined privilege mode. Multiple simultaneous interrupts destined for the same privilege mode are handled in the following -decreasing priority order: MEI, SEI, UEI, MSI, SSI, USI, MTI, STI, -UTI. Synchronous exceptions are of lower priority than all interrupts. +decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI. +Synchronous exceptions are of lower priority than all interrupts. \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})} |