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| author | Rishiyur S. Nikhil <nikhil@acm.org> | 2018-08-06 15:45:27 -0400 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-08-06 12:45:27 -0700 |
| commit | a533b92630e9715d90a2a35c4309c90d3820c98b (patch) | |
| tree | 579fddeb1c1869e1f8e8a4f3e5aa825a59486a61 /src/machine.tex | |
| parent | 816109de737352dbfb8b2fe47a373b448ee0a407 (diff) | |
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Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignment) (#220)
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 34b3b3d..56ac3e5 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1035,7 +1035,7 @@ the BASE field plus four times the interrupt cause number. For example, a machine-mode timer interrupt (see Table~\ref{mcauses}) causes the {\tt pc} to be set to BASE+{\tt 0x1c}. Setting MODE=Vectored may impose an additional alignment constraint on BASE, -requiring up to $4\times$MXLEN-byte alignment. +requiring $1\times$, $2\times$, or $4\times$MXLEN-byte alignment. \begin{commentary} When vectored interrupts are enabled, interrupt cause 0, which corresponds to |