Add counter-inhibit mechanism

1 files changed, 64 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 4fd6100..a18db60 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1682,6 +1682,70 @@ the memory-mapped {\tt mtime} register, or hard-wire the TM bit in
 and emulate this functionality in M-mode software.
 \end{commentary}
 
+\subsection{Machine Counter-Inhibit CSR ({\tt mcountinhibit})}
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{cccMcccccc}
+\instbit{31} &
+\instbit{30} &
+\instbit{29} &
+\instbitrange{28}{6} &
+\instbit{5} &
+\instbit{4} &
+\instbit{3} &
+\instbit{2} &
+\instbit{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{HPM31} &
+\multicolumn{1}{c|}{HPM30} &
+\multicolumn{1}{c|}{HPM29} &
+\multicolumn{1}{c|}{...} &
+\multicolumn{1}{c|}{HPM5} &
+\multicolumn{1}{c|}{HPM4} &
+\multicolumn{1}{c|}{HPM3} &
+\multicolumn{1}{c|}{IR} &
+\multicolumn{1}{c|}{0} &
+\multicolumn{1}{c|}{CY} \\
+\hline
+1 & 1 & 1 & 23 & 1 & 1 & 1 & 1 & 1 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Counter-inhibit register {\tt mcountinhibit}.}
+\label{mcountinhibit}
+\end{figure*}
+
+The counter-inhibit register {\tt mcountinhibit} is a 32-bit \warl\ register
+that controls which of the hardware performance-monitoring counters increment.
+The settings in this register only control whether the counters increment;
+their accessibility is not affected by the setting of this register.
+
+When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is
+clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register
+increments as usual.  When the CY, IR, or HPM{\em n} bit is set, the
+corresponding counter does not increment.
+
+If the {\tt mcountinhibit} register is not implemented, the implementation
+behaves as though the register were set to zero.
+
+\begin{commentary}
+When the {\tt cycle} and {\tt instret} counters are not needed, it is
+desirable to conditionally inhibit them to reduce energy consumption.
+Providing a single CSR to inhibit all counters also allows the counters to be
+atomically sampled.
+
+As all the harts on a processor core share a {\tt cycle} counter,
+so they share an {\tt mcountinhibit}.CY bit.
+
+Because the {\tt time} counter can be shared between multiple cores, it
+cannot be inhibited with the {\tt mcountinhibit} mechanism.
+\end{commentary}
+
 \subsection{Machine Scratch Register ({\tt mscratch})}
 
 The {\tt mscratch} register is an MXLEN-bit read/write register