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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:29:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 20:38:47 -0700 |
| commit | 92488700503a42b5077a668506a1c6452cb62791 (patch) | |
| tree | a4bd28b8ec7c51e98a0cf34e2313ab8e87d94795 /src/machine.tex | |
| parent | 7f0b39ad953e4023af587def0b21363ebfa5759a (diff) | |
| download | riscv-isa-manual-92488700503a42b5077a668506a1c6452cb62791.zip riscv-isa-manual-92488700503a42b5077a668506a1c6452cb62791.tar.gz riscv-isa-manual-92488700503a42b5077a668506a1c6452cb62791.tar.bz2 | |
Unused PMP fields are WARL 0, not WIRI
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 199b52c..ba1e1aa 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2782,7 +2782,7 @@ space, so the RV64 PMP address registers impose the same limit. \instbitrange{63}{54} & \instbitrange{53}{0} \\ \hline -\multicolumn{1}{|c|}{\wiri} & +\multicolumn{1}{|c|}{0 (\warl)} & \multicolumn{1}{c|}{address[55:2] (\warl)} \\ \hline 10 & 54 \\ @@ -2813,7 +2813,7 @@ described in the following sections. \instbit{0} \\ \hline \multicolumn{1}{|c|}{L (\warl)} & -\multicolumn{1}{c|}{\wiri} & +\multicolumn{1}{c|}{0 (\warl)} & \multicolumn{1}{c|}{A (\warl)} & \multicolumn{1}{c|}{X (\warl)} & \multicolumn{1}{c|}{W (\warl)} & |