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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 16:37:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 16:37:25 -0700 |
| commit | 8b5fbe5f5d1acd134cba5ad6f26f59b71cebdb84 (patch) | |
| tree | adcc3f84799612835d6f78366984b89cfd503eb5 /src/machine.tex | |
| parent | 3318c9e5c2594a64b19dcb6a6e3e0adc66172874 (diff) | |
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hart IDs must be unique
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 8ec2e61..ca9abbc 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -322,7 +322,7 @@ The {\tt mhartid} CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. This register must be readable in any implementation. Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, -but at least one hart must have a hart ID of zero. +but at least one hart must have a hart ID of zero. Hart IDs must be unique. \begin{figure*}[h!] {\footnotesize |